HARDWARE

connected to the system bus: CPU, RAM, clock, disk controllers (disks connect to their controllers), NIC, video card (monitor connects to video card), keyboard (port) controller, mouse (port) controller, printer (port) controller, modem (port) controller

system bus has 32 address lines, 32 data lines, IO line, RW line, interrupt line, interrupt acknowledgement line

registers in the CPU: PSW (processor status word), PC (program counter), SP (stack pointer), IR (instruction register), MAR (memory address register), MBR (memory buffer register), base register, limit register, general purpose registers

how the CPU uses the MAR and MBR registers and the RW line on the system bus to access RAM for reading and writing

hardware support for secure and protected multiprogramming: user-kernel mode of the CPU, base and limit CPU registers, clock hardware interrupts

PSW contains the user-kernel CPU mode bit, interrupts enabled-disabled bit

privileged instructions can be executed only in CPU kernel mode: IN, OUT, HALT, REBOOT, disable interrupts, load into base or limit register

the IN and OUT instructions are used read data and status information from devices (IN) and to send commands and data to devices (OUT), for example, reformat the disk drive, write to a disk block, read disk drive status, read a disk block

Do you see why these should be privileged instructions?

hardware interrupts:

• device raises interrupt line on system bus
• device waits for CPU to raise interrupt acknowledgement line
• device places interrupt ID on system bus
• CPU switches from user to kernel mode
• CPU disables interrupts
• CPU saves PC somewhere
• CPU accesses interrupt vector in low RAM to load into PC the address from interrupt vector entry for device ID
• CPU executes interrupt handler in OS kernel in CPU kernel mode
• when interrupt handler is finished CPU restores PC and enables interrupts and switches to user mode

software interrupts:

• TRAP instruction causes CPU to switch from user to kernel mode
• CPU disables interrupts
• CPU saves PC somewhere
• CPU accesses interrupt vector in low RAM to load into PC the address from interrupt vector entry for TRAP
• CPU executes interrupt handler in OS kernel in CPU kernel mode
• when interrupt handler is finished CPU restores PC and enables interrupts and switches to user mode

how the CPU uses the base and limit registers when executing a load/store instruction from/to RAM

CPU base and limit registers used when CPU in user mode

• each user process has its own base and limit values (stored in process table)
• CPU base and limit registers loaded from process table when a user process executes
• user program executes register load or store CPU instruction (address generated by compiler in range 0 to N-1 inclusive)
• CPU compares address with limit register contents, which is N
• if compares less than, then add base register contents
• send result (physical memory address) to RAM

numerical example

• Suppose the CPU is executing a user program. The PC register contains x. The base register contains y. The limit register contains z. The CPU is about to execute the following instruction.

  Load into register number r the contents of RAM at address q.

• Describe step-by-step how the CPU executes this instruction. Include how the CPU uses the base and limit registers as part of executing this instruction. What physical address gets sent to the RAM chips?
• Draw a diagram or picture with the parts labeled! (Various numbers are substituted for the variables x, y, z, r, and q with different answers depending on the numbers.)

clock chip interrupts let OS keep track of elapsed time so no one user process can ``hog'' the CPU (e.g., caught in infinite loop)

disks: controller and controller registers (command, status, data), platter, surface, track, cylinder, sector, disk arm, read-write heads

role of a device driver is to handle the very complicated details of device IO: reading and writing the device controller registers (command, status, data)

accessing device controller registers

• port-based: IN and OUT instructions
• memory-mapped: device controller registers ``occupy'' a portion of RAM

performing device IO

• busy waiting: while (!done) { ... }
• interrupt driven: controller interrupts after seek command done, then driver executes a loop to extract data 4 bytes at a time from the controller memory buffer
• DMA (direct memory access): one interrupt at the end of it all

home page: http://elvis.rowan.edu/~hartley/index.html
e-mail: hartley@elvis.rowan.edu